Cypress Semiconductor /psoc63 /CTDAC0 /CTDAC_CTRL

To prevent glitches after VALUE changes from propagating the output switch can be opened for DEGLITCH_CNT+1 clk_peri clock cycles.

Force CTDAC.CO6 switch open after each VALUE change for the set number of clock cycles.

Force CTB.COS switch open after each VALUE change for the set number of clock cycles.

Output enable, intended to be used during the Hold phase of the Sample and Hold when power cycling : 0: output disabled, the output is either:

• Tri-state (DISABLED_MODE=0)
• or Vssa (DISABLED_MODE=1 && CTDAC_RANGE=0)
• or Vref (DISABLED_MODE=1 && CTDAC_RANGE=1) 1: output enabled, CTDAC output drives the programmed VALUE

By closing the bottom switch in the R2R network the output is lifted by one LSB, effectively adding 1 0: Range is [0, 4095] * Vref / 4096 1: Range is [1, 4096] * Vref / 4096

DAC mode, this determines the Value decoding

0 (UNSIGNED12): Unsigned 12-bit VDAC, i.e. no value decoding.

1 (VIRT_SIGNED12): Virtual signed 12-bits’ VDAC. Value decoding: add 0x800 to the 12-bit Value (=invert MSB), to convert the lowest signed number 0x800 to the lowest unsigned number 0x000. This is the same as the SAR handles 12-bit ‘virtual’ signed numbers.

2 (RSVD2): N/A

3 (RSVD3): N/A

Select the output value when the output is disabled (OUT_EN=0) (for risk mitigation) 0: Tri-state CTDAC output when disabled 1: output Vssa or Vref when disabled (see OUT_EN description)

DSI strobe input Enable. This enables CTDAC updates to be further throttled by DSI. 0: Ignore DSI strobe input 1: Only do a CTDAC update if alllowed by the DSI stobe (throttle), see below for level or edge

Select level or edge detect for DSI strobe

• 0: DSI strobe signal is a pulse input, after a positive edge is detected on the DSI strobe signal the next DAC value update is done on the next CTDAC clock
• 1: DSI strobe signal is a level input, as long as the DSI strobe signal remains high the CTDAC will do a next DAC value update on each CTDAC clock.

• 0: CTDAC IP disabled off during DeepSleep power mode
• 1: CTDAC IP remains enabled during DeepSleep power mode (if ENABLED=1)

0: CTDAC IP disabled (put analog in power down, open all switches) 1: CTDAC IP enabled